The First Aircraft Institute of AVIC Chooses T-VEC for Model-Based Testing
T-VEC Technologies, producer of the world's most
advanced model-based analysis, verification, and test generation tools and
technologies, announced that The First Aircraft Institute of AVIC (FAI), a leading Chinese aircraft research institute, has selected their T-VEC Technologies RAVE and Vector Generation Systems solutions to develop software-intensive systems.
FAI is the largest aircraft design and research institute in the People's Republic of China, and was founded in November 1961 and its headquarters is located at Yanliang, Shaanxi Province. FAI is engaged in the development of large and medium-sized civil aircraft.
T-VEC develops some of the world's most advanced
model-based verification and testing tools. Our technologies help detect
problems early on in the development lifecycle, when they are least expensive
to correct, preventing them from having negative impact on downstream
development activities. USP of T-VEC software is that it verifies and validates
the coding for all mission critical applications used in aerospace, automotive
and similar industries where simulation is required.
The T-VEC tool suite is composed of three applications:
T-VEC Tabular Modeler (TTM), T-VEC Tester for Simulink, and T-VEC Vector
Generation System (VGS).
TTM plus T-VEC VGS provides an easy to use graphical interface for creating precise and consistent requirements and using these as a basis for: requirement management, automated requirements defect detection, automated test vector and test driver creation and execution, and requirements-to-test traceability. TTM is also integrated with IBM/Rational's® DOORS® product to support the capturing and maintenance of an association between informal human language requirements text and the more formal and analyzable representation of the functional requirements that are the focus of TTM.
The T-VEC Tester for Simulink and Stateflow plus T-VEC VGS performs model analysis, proof of properties, test vector generation, test driver and harness generation for the MathWorks® RTW and MATLAB simulator, test results analysis, and report generation. The T-VEC Tester provides fully automated execution through a GUI integrated within MATLAB, or through command interface for batch processing.
T-VEC VGS is the the theorem-proving-based test vector generation engine used by both TTM and the
T-VEC Tester to support model analysis, proving system properties, test vector
generation, and test drivers for virtually any language supporting test
execution in simulation, host, or target test environments. It also has
comprehensive report generation capabilities, supporting fully hyperlinked
documentation, model error analysis, status, and metrics.
For more details see www.t-vec.com.