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T-VEC develops some of the world's most advanced model-based verification and testing tools. In development for over 15 years, these tools automate error analysis and test generation for both requirements and design models.

They detect problems early when they are least expensive to correct and prevent them from impacting downstream development activities. During verification they automate the typically labor-intensive and error-prone test design process to produce more effective and comprehensive tests.

View Video: Overview of T-VEC's Tool Suite

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RAVE is a proven method and integrated toolset for requirement-based defect prevention and automated testing.

It includes the T-VEC Tabular Modeler for requirements capture, management, and automated analysis to identify problems before they impact the software.

T-VEC's model-based functional test generation system automates the typically manual and error-prone testing activities including test generation and test driver generation.

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T-VEC Tester for Simulink and Stateflow (sl2tvec)

The T-VEC Tester for Simulink and Stateflow (sl2tvec) analyzes Simulink and Stateflow models for errors, and generates comprehensive test suites for verifying the models and their implementations.

Test scripts or drivers are automatically generated for executing tests in Matlab simulator and in the embedded targets running code generated with RTW.

  • Unit, integration and system level tests (MC/DC)
  • Model defect identification
  • Test harnesses for simulation and execution on target
  • Tests traceable to model and requirements
  • Integration with code coverage tools such as LDRA

More about Simulink and Stateflow Testing