T-VEC Technologies, producer of some of the world's most advanced model-based analysis, verification, and test generation tools and technologies, announces the integration of the T-VEC Vector Generation System (VGS) with Vector Software’s VectorCAST unit  integration software test platform.  Test vectors produced by the VGS test vector generator can now be automatically converted into VectorCAST test scripts using the VGS test driver generation technology. The tests can then be executed directly on the automatically generated VectorCAST harnesses, either within VectorCAST’s Graphical User Interface environment or via the “command line” version of the VectorCAST technology. These same tests can also be executed against many different target environments utilizing VectorCAST’s Runtime Support Package (RSP).

This integration came about at the request of a major aerospace company. This company had a requirement to provide test coverage evidence for the code generated from their Simulink models. As a T-VEC VGS user, this aerospace company can now take advantage of Vector Software’s VectorCAST technology to analyze the code coverage effectiveness of the test vectors produced directly from Simulink/Stateflow models by VGS. In addition, VectorCAST can also be used to analyze the code coverage of software requirement, when those requirements are captured in T-VEC’s TTM (T-VEC Tabular Modeler) requirements modeling tool. This requirements-based capability effectively meets the needs of the many companies in the commercial aerospace domain that have requirements-based testing as a mandated part of DO-178B certification.

Finally, VectorCAST users now have the option of adding model-based verification to their code-based testing capabilities. By employing T-VEC ‘s TTM, and/or Simulink/Stateflow along with T-VEC’s Simulink Tester, VectorCAST users can create one or more oracles of correct functionality that can be used as the basis for their verification testing efforts.

About Vector Software

Vector Software, Inc. is the leading independent provider of automated software testing tools for developers of safety-critical embedded applications. Vector Software’s VectorCAST line of products, automate and manage the complex tasks associated with unit, integration, and system level testing. The VectorCAST tools support the C, C++, and Ada programming languages. For more details see www.vectorcast.com.

About T-VEC

T-VEC develops some of the world's most advanced model-based verification and testing tools. Our technologies help detect problems early on in the development lifecycle, when they are least expensive to correct, preventing them from having negative impact on downstream development activities. USP of T-VEC software is that it verifies and validates the coding for all mission critical applications used in aerospace, automotive and similar industries where simulation is required.

General Description

The T-VEC tool suite is composed of three applications: T-VEC Tabular Modeler (TTM), T-VEC Tester for Simulink, and T-VEC Vector Generation System (VGS). 

TTM plus T-VEC VGS provides an easy to use graphical interface for creating precise and consistent requirements and using these as a basis for:  requirement management, automated requirements defect detection, automated test vector and test driver creation and execution, and requirements-to-test traceability. TTM is also integrated with IBM/Telelogic’s DOORS^® product to support the capturing and maintenance of an association between informal human language requirements text and the more formal and analyzable representation of the functional requirements that are the focus of TTM.

The T-VEC Tester for Simulink and Stateflow plus T-VEC VGS performs model checking, test vector generation, test driver and harness generation for the MathWorks^® RTW and MATLAB simulator, test results analysis, and report generation. The T-VEC Tester provides fully automated execution through a GUI integrated within MATLAB, or through command interface for batch processing.

T-VEC VGS is the core engine used by both TTM and the T-VEC Tester to support model analysis, proving system properties, test vector generation, and test drivers for virtually any language supporting test execution in simulation, host, or target test environments. It also has comprehensive report generation capabilities, supporting fully hyperlinked documentation, model error analysis, status, and metrics. For more details see www.t-vec.com.