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Simulink Tester 3.0 with Stateflow Support Available


  • Beta release of the Simulink Tester for T-VEC with Stateflow support is now available for download
  • Supports Simulink Release 13 and Release 14
  • Systematic, comprehensive test generation from Simulink models
  • Model checking that identifies model defects
  • Unit, integration, and system-level test generation with Path, Decision and Condition test coverage (MC/DC)
  • Test sequences for verifying dynamic systems
  • Assertions for proving properties about the model
  • Integration with code coverage tools
  • Measurement and status reports for tracking project status
  • Suitable for software certification under the DO-178B guidelines


T-VEC Tester for Simulink provides an integrated solution for model analysis, automatic test generation, test execution, and results analysis. It analyzes every path throughout the model hierarchy and generates test vectors that exercise the path boundaries. The test selection process produces unit, integration, and system-level test vectors most effective in revealing both decision and computational errors in logical, integer, and floating-point domains. Unreachable paths and other model errors are identified with hyperlinks to the Simulink model elements involved. Test sequence vectors support testing multiple sample times to verify dynamic system response.

T-VEC Tester for Simulink is used by engineers who develop and test embedded applications with Simulink. It analyzes the compiled version of the Simulink model generated by the Real-Time Workshop to identify defects in the model and generate comprehensive test suites. Test drivers are automatically generated for executing the tests against the C source code generated by the Real-Time Workshop or for driving simulations within MATLAB. Testing activities from test design to test result analysis are fully automated. . Resulting code is suitable for software certification for safety critical applications based on the DO-178B guidelines.